1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a self-timed random access memory (STRAM) device in the form of a chip, having a function of generating a write signal (pulse) within the chip in response to an external clock and an external write enable signal.
A conventional static RAM (SRAM) carries out a write operation of data in response to an external write signal (pulse) with respect to a memory cell selected by an external address data. In this case, since both the address data and the write pulse are asynchronously applied to the SRAM, a timing of the application of the write pulse must be regulated outside the memory (chip) in a write-in of data. In practice, however, it is relatively difficult to regulate the application timing externally. Accordingly, measures are generally taken to give some time margin to the application timing. Thus, the SRAM poses a when high-speed operation is demanded. To cope with this, the above STRAM device has been developed.
2. Description of the Related Art
A typical STRAM device in the form of a chip automatically defines a cycle for carrying out a predetermined function, e.g., a read cycle, a write cycle or the like, in the chip in response to an external clock and an external write enable signal. For example, assuming that the read cycle and the write cycle are alternately defined at every rise of the clock, data which has been read is output in the former cycle and data to be written in is input in the latter cycle. In this case, the data output must be completed by the end of the read cycle. In practical operation, however, data is still being output even at the rise of the clock in the next cycle, i.e., write cycle, due to small delay in the read operation. On the other hand, when the write cycle begins at the rise of the clock, the write data is taken into the chip. Namely, both the "data output" and "data input" states are present at the same time. Therefore, the above conventional STRAM device must have a data input path (input terminal) and a data output path (output terminal) which are separate from each other.
On the other hand, it is known that, in an ordinary semiconductor device in the form of a chip, the space occupied by a terminal or terminals on the chip is extremely large compared with that occupied by other integrated circuit portions on the chip. This means that, the more the terminals are increased in number, the larger the whole circuit becomes in scale. Accordingly, the above STRAM device having both an input terminal and an output terminal is not suitable due to its large size.
Also, the above STRAM device generates a write pulse within the chip in response to the rise of the clock indicating a beginning of the write cycle. In this case, the write data supplied to in the chip and latched therein at the rise of the clock, is written in a memory cell selected based on external address data supplied to the chip at the rise of the clock, when the write pulse is generated. Namely, the access of write data is carried out immediately after the write enable signal is latched in the chip at the rise of the clock.
Therefore, since the writing of data into a cell selected at the rise of the clock is carried out without fail, it becomes impossible to cancel the write operation halfway. This results in a disadvantage as follows. Assuming that the data write operation is carried out with respect to a memory cell of address A, address data corresponding to the address A is input into the memory device. In this case, a check of whether or not the input address data really indicates the address A, i.e., an address parity check, is carried out in the memory device. Naturally, since the parity check requires some time, the result of the check is output at a certain time after the rise of the clock. When the parity check result indicates correct data, no problem occurs. However, in a case, e.g., where the input address data indicates an address B, a problem occurs in that the input data is written in a wrong cell corresponding to the address B, because the write operation to the cell of address A is carried out at the rise of the clock.
Furthermore, since the input data is composed of several bits of data, the above STRAM device requires a plurality of data input terminals corresponding to the number of data bits. As a result, the space occupied on the chip by the input terminals becomes relatively large. This leads to an increase in the scale of the whole circuit device, and thus, is not preferable.